1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a transistor with a recess gate and a method for fabricating the same.
2. Description of the Related Art
As the degree of integration of a semiconductor memory device, such as a DRAM, increases, an area occupied by a transistor gradually decreases. Therefore, as the channel length of the transistor is shortened, a short channel effect occurs. In particular, if the short channel effect occurs in a cell transistor, which is adopted in the memory cell of a DRAM, leakage current of the memory cell increases, and a refresh characteristic deteriorates. According to this fact, a recess gate structure capable of suppressing the short channel effect, even when the degree of integration of a DRAM increases, has been suggested.
Recently, a method of applying the recess gate structure to improve driving performance of a transistor formed in a peripheral region has been suggested.
FIG. 1 is a cross-sectional view illustrating a conventional transistor with a conventional recess gate structure.
Referring to FIG. 1, a recess 12 is defined in a semiconductor substrate 11. A gate dielectric layer 13 is formed on a surface that defines the recess 12. A recess gate structure, including a silicon electrode 14, is formed on the gate dielectric layer 13 and fills the recess 12. A metal electrode 15 is formed on the silicon electrode 14 and a gate hard mask layer 16 is formed on the metal electrode 15. Source/drain regions 17 are formed in the semiconductor substrate 11 on both sides of the recess gate structure.
In FIG. 1, the silicon electrode 14 includes polysilicon and is doped with an impurity to have a conductivity. For example, after depositing undoped polysilicon to fill the recess 12, the impurity is doped. The impurity may include a N-type impurities or a P-type impurity, depending on a desired type of transistor. For example, an NMOSFET includes N-type polysilicon while a PMOSFET includes P-type polysilicon.
FIGS. 2A and 2B are views illustrating impurity doping methods for a silicon electrode according to the conventional art. FIG. 2A illustrates an ion beam implantation method, and FIG. 2B illustrates a plasma doping method.
When doping impurities using the ion beam implantation method, ion beam implantation method may be performed by setting a projection range Rp to a deep zone of a recess as indicated by the reference symbol {circle around (1)}. However, in the ion beam implantation method, a problem may be caused in that a penetration phenomenon is likely to occur as indicated by the reference symbols {circle around (2)} and {circle around (3)}.
In the plasma doping (PLAD) method, as is generally known in the art, the surface of a silicon electrode has a greatest doping concentration and impurities are diffused downward. Therefore, as the height of the silicon electrodes increases, doping efficiency abruptly decreases. Therefore, in the recess gate structure, while doping may be sufficiently performed on the surface and up to an intermediate zone {circle around (4)}, it is difficult to sufficiently perform doping up to a deep zone {circle around (5)} of a recess.